Ion implantation is a standard technique for introducing conductivity-altering impurities into semiconductor workpieces. A desired impurity material is ionized in an ion source, the ions are accelerated to form an ion beam of prescribed energy, and the ion beam is directed at the surface of the workpiece. The energetic ions in the beam penetrate into the bulk of the workpiece material and are embedded into the crystalline lattice of the workpiece material to form a region of desired conductivity.
Flash memory is a type of computer memory that can be electrically erased and reprogrammed. This sort of memory is used in memory cards and universal serial bus (USB) flash drives, for example. A specific type of flash memory is referred to as NAND (Not And). This uses tunnel injection for writing and tunnel release for erasing. Tunneling alters the placement of electrons within the flash memory. Charge carriers may be injected into a conductor through a thin insulator layer to program the flash memory. Charge carriers also may be released from the conductor through a thin insulator layer to erase the flash memory.
FIG. 1 is a cross-sectional diagram of a flash stack. The flash stack 300 includes a first oxide layer 301, a first nitride layer 302, and a second oxide layer 303 that make up the oxide-nitride-oxide (ONO) tunnel stack 310 or ONO tunneling dielectric. The first nitride layer 302 may be approximately 70 nm in thickness. The flash stack 300 further includes a second nitride layer 304 that functions as a charge storage layer. This second nitride layer 304 may be between approximately 1200 to 2000 Angstroms in thickness. In one instance, this second nitride layer 304 is SixNy wherein the x and y values can vary according to SixNy deposition plasma ratios. SixNy may be abbreviated SiN. A third oxide layer 305 functions as a blocking oxide and a poly gate 306 is disposed on top. The flash stack 300 acts as a gate of the device which has a source 307 and a drain 308, both of which may be n+ and are disposed in a channel 309. The channel 309 may be a p-well.
In a molecule, energy bands exist based on energy levels of the electrons because the electrons of each atom will act upon other adjacent electrons. Thus, the individual atomic orbital states will split into energy bands in a molecule. A band gap, for example, is the energy difference between the valence band and the conduction band. This band gap is an energy region where no electron orbitals are found. Electrons are able to jump between these two bands across the band gap by acquiring or losing energy. The width of any band gap or band is dependent on the properties of the atomic orbitals.
The second nitride layer 304 typically has a band gap of approximately 2.1 eV. The first nitride layer 302 may have substantially similar properties. At least the second nitride layer 304 acts as a tunneling barrier as this has a significantly higher band gap than an oxide layer. To program the flash stack 300, a positive voltage is applied to the poly gate 306 to tunnel electrons from the channel 309 or other locations into the second nitride layer 304. Electrons that go into the second nitride layer 304 may, in theory, stay there indefinitely because there is no path for the electrons to escape. To erase the flash stack 309, a negative voltage is applied to the poly gate 306 and holes tunnel and recombine with electrons in the second nitride layer 304. In another instance, the electrons may tunnel and drain to ground.
If a positive voltage is applied to the poly layer 306 it induces a field under the gate region in the channel 309. This is called a program cycle. If this applied voltage is higher than the required threshold voltage for a given device, to the electrons from the source 307 will transfer to the drain region 308. In the process the electrons also will tunnel through the ONO tunnel stack 310 toward the top of the poly gate 306 and get trapped in the second nitride layer 304. The accumulation of charge in the second nitride layer 304 will, thus, provide and store a value of “1.” This value is stored until erased by a refreshing process using a voltage of the opposite sign. The retention of this charge in the second nitride layer 304 for an infinite duration is the essence of the “charge-trap flash.” The ability of the second nitride layer 304 to retain the tunneled electrons is a factor in the performance and reliability of the flash stack 300. With the advent of scaling the layers of the ONO tunnel stack 310 have become extremely thin. This allows electrons to slowly diffuse back into the channel 309 or into the ONO tunnel stack 310. Thus, with time the charge trap layers may lose enough electrons (charge) through the ONO tunnel stack 310 that the flash stack 300 does not hold the value of “1” anymore. Therefore, there is a need to enable better charge retention capacity of the second nitride layer 304.
In a similar fashion as explained above, if the desired value to be stored is “0” then an appropriate negative voltage is applied to the poly gate 306. This enables holes from the channel 309 to tunnel through the ONO tunnel stack 310 and get stored in the second nitride layer 304. Then the flash memory will store a value of 0. The same retention capacity of the second nitride layer 304 as explained above works for holes as well as electrons. The voltages applied to the poly gate 306 may be between approximately 10-15 V and scaled appropriately with the thicknesses, materials, and technology node of the flash stack 300. A positive voltage is applied for tunneling electrons and negative voltage for tunneling holes.
To erase the stored value in a stack a voltage of opposite sign is applied to the poly gate 306 and the electrons and holes are passivated by charges of opposite type. Repeatedly performing the program and erase functions degrades the integrity of the ONO tunnel stack 310 and also the second nitride layer 304. This type of damage further reduces charge retention capacity of the second nitride layer 304 and makes the layers of the ONO tunnel stack 310 leaky. Therefore there is a need to enhance the charge storage capability of the second nitride layer 304.
Feature sizes in conventional flash memory, including NAND flash memory, have reached scaling limits. It is becoming more difficult to shrink these types of memory. Some tunneling oxide layers, such as the first oxide layer 301, may be less than approximately 12 Angstroms in thickness. Such low thicknesses may mean that the ONO tunnel stack 310 has become leaky and not in the Fowler-Nordheim (FN) tunneling regime where interactions between charge carriers and atoms affect tunneling, but rather in the direct tunneling regime. Therefore, NAND flash memory manufacturers are implementing a “charge-trap” integration scheme. The present method to enable charge trap flash memory is to deposit film layers in the flash stack 300, including the second nitride layer 304, that have a higher band gap. Such a method has limitations. Deposited films show an increase in band gap when the ratio of Si in the SiN is increased. But there is an intrinsic upper value to this ratio increase because beyond a certain limit the dielectric breakdown strength of the nitride will be compromised due to “k” centers in the SiN and the crystal structure of the SiN. Furthermore, the etch rate and etch selectivity of this layer will increase, which leads to difficulty of etching the flash stack 300. Accordingly, there is a need in the art for an improved method of charge trapping, and, more particularly, of using ion implantation to enhance charge trapping for flash memory.